DICTAM

Objectives

DICTAM's objective is to develop new processor architectures, algorithms and integrated circuits for real-time image processing, and to corroborate their advantages using programmable hardware demonstrators applied to selected real-case examples: real-time video compression, image authenticity / integrity verification, and various visual inspection and motion scene evaluation tasks. DICTAM´s success relies on three interlaced objectives: 1) Design of custom Analog Programmable Array Processors (APAPs) Focal Plane APAs (FPAPAPs), and image memory devices with optimum trade-off among area efficiency, accuracy, speed, and power consumption. 2) Development of optimum hardware / software system architectures hosting the new devices as well as conventional PSPs. 3) Development of image processing algorithms for the new processing systems, including adaptive partitioning of the processing tasks among APAPs and DSPs.

Description of work

The technical work has been structured into four workpackages. WP1 ( Design and test of chip-sets): Development of circuit strategies for optimum trade-offs among speed, accuracy, area efficiency, And power consumption of Analog Programmable Array Processors (APAPs), Focal Plane (FPAPAPs), and image memory devices (Analog RAMs) in 0.35 um and/or 0.25um CMOS technologies. Characterization of CMOS-compatible optical sensors and selection of an optimum alternative for FPAPAPs. Design and test of a 128 x 18 general-purpose APAP chip and 256 x 256 ARAM to be used in a video computing demonstrator. Design and test of a dedicated 128 x 128 FPAPAP CMOS chip with embedded image acquisition to be used in an intelligent visual device demonstrator. Wp2 (Design an test of Analogic Cellular Engine (ACE) boards): Specification, design and test of different hardware platforms hosting alternative combinations of the chips developed in WP1, conventional Digital Signal Processors (DSPs), and conventional image acquisitin devices. Development of the software environment required for the control and optimum exploitation of the new ACE architectures. Development of learning and fault-tolerant algorithms for robust applications under the expected residual parametric errors of the analog circuitry. Wp3 (Video Computing): Development of ACE-compatible algorithms for video coding, authenticity, and integrity verification, and of higher level algorithms for selected video computing applications based on the new computing archiectures. Wp4 (Embedded Intelligent Visual Devices): Specification of the FPAPAP functionality required for visual-inspection and motion-environment event detection applications. Development of algorithms for environmental surveillance, intelligent scannin, hand-held video conference, and of higher level algorithms for visual-inspection applications defined by industrial partners.

Milestones and expected results

The milestones expected from DICTAM include specific purpose chips, printed circuit boards, software, and algorithms for selected application cases to be used as demonstrators of the potential of these new processing architectures. A stand-alone system demonstrator will be developed for visual inspection and motion picture event detection applications. Developed knowledge will be properly disseminated in order to spread the resulting computing advantages to all related application fields.Dynamic Image Computing Using Tera-Speed Analog Visual Microprocessors