MTA SZTAKI Hungarian Academy of Sciences Institute for Computer Science and Control

Publication without a category

Statistical error modeling of CNN-UM architectures: The binary case

Authors: Földesy, Péter
Editor: Tetzlaff, R
Date: 2002.
Published by: Cellular Neural Networks and Their Applications. Proceedings of the 7th IEEE International Workshop (Page: 4)

Integrated CMOS sub-THz imager array

Authors: Földesy, Péter; Zarándy, Ákos
Date: 2012.
Published by: 13th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA’2012

Behavioral modeling concept and practice of CNN-UM VLSI implementations

Authors: Földesy, Péter; Rodíguez-Vázquez, A.
Editor: Porra, V
Date: 2001.
Published by: Circuit paradigm in the 21st century. ECCTD '01. Proceedings of the 15th European conference on circuit theory and design. Espoo, 2001. Vol. 3. (Page: 9)

PDE based histogram modification with embedded morphological processing of the level-sets

Authors: Cserey, György; Rekeczky, Csaba; Földesy, Péter
Editor: Tetzlaff, R
Date: 2002.
Published by: Cellular Neural Networks and Their Applications. Proceedings of the 7th IEEE International Workshop (Page: 3)

Moving object traking on panoramic images

Authors: Földesy, Péter; Szatmári, István; Zarándy, Ákos
Editor: Tetzlaff, R
Date: 2002.
Published by: Cellular Neural Networks and Their Applications. Proceedings of the 7th IEEE International Workshop (Page: 6)

The new framework of applications: the Aladdin system

Authors: Zarándy, Ákos; Rekeczky, Csaba; Földesy, Péter; Szatmári, István
Date: 2003.
Published by: JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS (Page: 7)

Analogic cellular PDE machines

Authors: Rekeczky, Csaba; Szatmári, István; Földesy, Péter; Roska, Tamás
Editor: Fogel, D
Date: 2002.
Published by: Proceedings of the 2002 IEEE World Congress on Computational Intelligence (WCCI 2002) Honolulu

Image processing library for the ALADDIN visual computer

Authors: Szatmári, István; Földesy, Péter; Rekeczky, Csaba; Zarándy, Ákos
Editor: Tetzlaff, R
Date: 2002.
Published by: Cellular Neural Networks and Their Applications. Proceedings of the 7th IEEE International Workshop (Page: 5)

Computing on silicon with trigger-waves: experiments on CNN-UM chips

Authors: Rekeczky, Csaba; Szatmári, István; Földesy, Péter
Date: 2001.
Published by: IEEE international symposium on circuits and systems. ISCAS 2001. Sydney, 2001. Vol. 3. (Page: 4)

CNN technology in action

Authors: Zarándy, Ákos; Espejo, S.; Földesy, Péter; Kék, László; Linán, G.; Rekeczky, Csaba; Rodriguez-Vázquez, A.; Roska, Tamás; Szatmári, István; Szirányi, Tamás; Szolgay, Péter
Date: 2000.
Published by: Proceedings of the 6th IEEE international workshop on cellular neural networks and their applications. (CNNA 2000). Catania, 2000. (Page: 7)

Sructure reconfigurability of the CNNUC3 for robust template operation

Authors: Földesy, Péter; Linán, G.; Rodriguez-Vázquez, A.; Espejo, S.; Dominguez-Castro, R.
Date: 2000.
Published by: Proceedings of the 6th IEEE international workshop on cellular neural networks and their applications. (CNNA 2000). Catania, 2000. (Page: 2)

An analogic CNN engine board with the 64x64 analog I/O CNN-UM chip

Authors: Szatmári, István; Zarándy, Ákos; Földesy, Péter; Kék, László
Date: 2000.
Published by: The 2000 IEEE international symposium on circuits and systems. Emerging technologies for the 21st century. ISCAS 2000. Geneva, 2000. Vol. 2. (Page: 1)

A development system for prototyping and interfacing CNN chips and for analogic algorithm design

Authors: Zarándy, Ákos; Roska, Tamás; Szolgay, Péter; Földesy, Péter; Zöld, S.
Editor: Roska, T; Rodriguez-Vázquez, A
Date: 2000.
Published by: Towards the visual microprocessor. VLSI design and the use of cellular neural network universal machines. (Page: 3)

Realization of non-linear templates using the CNNUC3 prototype

Authors: Linán, G.; Földesy, Péter; Rodríguez-Vázquez, A.; Espejo, S.; Dominguez-Castro, R.
Date: 2000.
Published by: Proceedings of the 6th IEEE international workshop on cellular neural networks and their applications. (CNNA 2000). Catania, 2000. (Page: 2)

Object oriented image segmentation on the CNNUC3 chip

Authors: Földesy, Péter; Linan, G.; Rodriguez-Vázquez, A.; Espejo, S.; Dominguez-Castro, R.
Date: 2000.
Published by: Proceedings of the 6th IEEE international workshop on cellular neural networks and their applications. (CNNA 2000). Catania, 2000. (Page: 2)

CNN-UM architektúrák hibamodellezése és alkalmazhatóságuk kiterjesztése - modellezés, analízis és műveleti szintézis

Authors: Földesy, Péter
Date: 2000.

Implementation of non-linear templates using a decomposition technique by a 0.5mm CMOS CNN universal chip

Authors: Linán, G.; Földesy, Péter; Rodríguez-Vázquez, A.; Espejo, S.; Dominiguez-Castro, R.
Date: 2000.
Published by: The 2000 IEEE international symposium on circuits and systems. Emerging technologies for the 21st century. ISCAS 2000. Geneva, 2000. Vol. 2. (Page: 4)

PDE-based histogram modification with embedded morphological processing of the level-sets

Authors: Cserey, György; Rekeczky, Csaba; Földesy, Péter
Date: 2003.
Published by: JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS (Page: 5)

A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips

Authors: Földesy, Péter; Rodríguez-Vázquez, Á.
Date: 2002.
Published by: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS (Issue no.: 2, Page: 1)

A 3-D chip architecture for optical sensing and concurrent processing

Authors: Rodríguez-Vázquez, A.; Carmona, R.; Domínguez Matas, C.; Suárez-Cambre, M.; Brea, V.; Pozas, F.; Linán, G.; Földesy, Péter; Zarándy, Ákos; Rekeczky, Csaba
Editor: Berghmans, F.; Mignani, A. G.; van Hof, C. A.
Date: 2010.
Published by: Optical sensing and detection. Brussels, 2010. (Proceedings of SPIE 7726.) (Page: 7)

Cellular multi-core processor carrier chip for nanoantenna integration and experiments

Authors: Zarándy, Ákos; Földesy, Péter; Carmona, R.; Rekeczky, Cs.; Bean, J. A.; Porod, W.
Editor: Baatar, C.; Porod, W.; Roska, Tamás
Date: 2010.
Published by: Cellular nanoscale sensory wave computing. (Page: 1)

3D multi-layer vision architecture for surveillance and reconnaissance applications

Authors: Földesy, Péter; Carmona-Galan, R.; Zarándy, Ákos; Rekeczky, Cs.; Rodríguez-Vázquez, A.; Roska, Tamás
Date: 2009. 08. 23.
Published by: ECCTD 2009. 19th European conference on circuit theory and design. Antalya, 2009. (Page: 1)

Displacement calculation algorithm on a heterogeneous multi-layer cellular sensor processor array

Authors: Zarándy, Ákos; Fekete, D.; Földesy, Péter; Soós, G.; Rekeczky, Cs.
Editor: Roska, Tamás; Gilli, Marco; Zarándy, Ákos
Date: 2010. 02. 03.
Published by: 12th international workshop on cellular nanoscale networks and their applications. CNNA 2010. Berkeley, 2010. (Page: 1)

Digital processor array implementation aspects of a 3D multi-layer vision architecture

Authors: Földesy, Péter; Carmona-Galan, R.; Zarándy, Ákos; Rekeczky, Cs.; Rodríguez-Vázquez, A.; Roska, Tamás
Editor: Roska, Tamás; Gilli, Marco; Zarándy, Ákos
Date: 2010. 02. 03.
Published by: 12th international workshop on cellular nanoscale networks and their applications. CNNA 2010. Berkeley, 2010. (Page: 3)

VISCUBE: a multi-layer vision chip

Authors: Zarándy, Ákos; Rekeczky, Csaba; Földesy, Péter; Carmona-Galán, Ricardo; Linán-Cembrano, Gustavo; Sós, Gergely; Rodríguez-Vázquez, Angel; Roska, Tamás
Editor: Zarándy, Ákos
Date: 2011.
Published by: Focal-plane sensor-processor chips. (Page: 1)

Active wave computing on silicon: chip experiments

Authors: Rekeczky, Csaba; Petrás, István; Szatmári, István; Földesy, Péter
Date: 2003.
Published by: Circuit Theory and Design. Proceedings of the 16th European Conference ECCTD'03. Vol. 2. (Page: 4)

Analysis of 2D operators on topographic and non-topographic processor architectures

Authors: Zarándy, Ákos; Rekeczky, Csaba; Földesy, Péter
Date: 2008.
Published by: CNNA 2008. 11th international workshop on cellular neural networks and their applications. Santiago de Compostella, 2008. (Page: 5)

Digital micromirror device (DMD) projector based test bench for vision chips

Authors: Gergelyi, Domonkos; Földesy, Péter
Editor: Roska, Tamás; Gilli, Marco; Zarándy, Ákos
Date: 2010. 02. 03.
Published by: 12th international workshop on cellular nanoscale networks and their applications. CNNA 2010. Berkeley, 2010. (Page: 4)

Per-pixel integration time controlled image sensor

Authors: Zarándy, Ákos; Földesy, Péter; Roska, Tamás
Date: 2005.
Published by: ECCTD�05. Proceedings of the 2005 European conference on circuit theory and design. Cork, 2005. (Page: 1)

Various implementations of topographic, sensory, cellular wave computers

Authors: Zarándy, Ákos; Földesy, Péter; Szolgay, Péter; Tőkés, Szabolcs; Rekeczky, Csaba; Roska, Tamás
Date: 2005.
Published by: ISCAS 2005. IEEE international symposium on circuits and systems. Kobe, 2005. (Page: 5)

Clusterable cellular visual microprocessor

Authors: Földesy, Péter; Zarándy, Ákos; Rekeczky, Csaba
Date: 2008.
Published by: CNNA 2008. 11th international workshop on cellular neural networks and their applications. Santiago de Compostela, 2008. (Page: 1)

Digital implementation of the cellular sensor-computers

Authors: Földesy, Péter; Zarándy, Ákos; Rekeczky, Csaba; Roska, Tamás
Date: 2006.
Published by: International Journal of Circuit Theory and Applications (Page: 4)

Trends in design of massively parallel coprocessors implemented in digital ASICs

Authors: Földesy, Péter
Date: 2004.
Published by: Neural Networks, 2004. Proceedings. IEEE International Joint Conference IJCNN'04, Vol. 4. (Page: 3)

Configurable 3D-integrated focal-plane sensor-processor array architecture

Authors: Földesy, Péter; Zarándy, Ákos; Rekeczky, Csaba
Date: 2008.
Published by: International Journal of Circuit Theory and Applications (Issue no.: 5, Page: 5)

3D integrated scalable focal-plane processor array

Authors: Földesy, Péter; Zarándy, Ákos; Rekeczky, Csaba; Roska, Tamás
Date: 2007.
Published by: ECCTD 2007. European conference on circuit theory and design. Sevilla, 2007. (Page: 9)

High performance processor array for image processing

Authors: Földesy, Péter; Zarándy, Ákos; Rekeczky, Csaba; Roska, Tamás
Date: 2007.
Published by: ISCAS 2007. IEEE international symposium on circuits and systems. New Orleans, 2007. (Page: 1)

Distance preserving 1D turing-wave models via CNN, implementation of complex-valued CNN and solving a simple inverse pattern problem (detection)

Authors: Tóth, Gábor András; Földesy, Péter; Roska, Tamás
Date: 1996.
Published by: 1996 fourth IEEE international workshop on Cellular Neural Networks and their applications proceedings. CNNA-96. Seville, 1996. (Page: 1)

Functional measurements of the first analog input/output CNN universal chip. (Research report of the Analogical and Neural Computing Laboratory, DNS-4-1997.)

Authors: Zarándy, Ákos; Cruz, M.; Szolgay, Péter; Földesy, Péter; Chua, LO; Roska, Tamás
Date: 1997.
Published by: Functional measurements of the first analog input/output CNN universal chip. (Research report of the Analogical and Neural Computing Laboratory, DNS-4-1997.)

Distance preserving 1D turing-pattern models via CNN, implementing of complex-valued CNN, and solving a simple inverse pattern problem (detection).( Research report of the Analogical and Neural Computing Laboratory, DNS-3-1996.)

Authors: Tóth, Gábor András; Földesy, Péter; Roska, Tamás
Date: 1996.
Published by: Distance preserving 1D turing-pattern models via CNN, implementing of complex-valued CNN, and solving a simple inverse pattern problem (detection).( Research report of the Analogical and Neural Computing Laboratory, DNS-3-1996.)

The first steps toward the application of the CNN chips

Authors: Szolgay, Péter; Földesy, Péter; Gubai, GY; Kukoda, G.
Editor: Sincák, P
Date: 1996.
Published by: Intelligent technologies. Proceedings of the 1-st Slovak neural networks symposium. Herl'any, 1996. Vol. 2. (Page: 2)

A CNN engine board

Authors: Földesy, Péter; Szolgay, Péter
Date: 1997.
Published by: ECCTD '97. Design automation day on cellular computing architectures for multimedia and intelligent image sensors. Budapest, 1997. (Page: 1)

A CNN platform to a discrete-time cellular neural network universal machine chip. (Research report of the Analogical and Neural Computing Laboratory DNS-12-1995.)

Authors: Földesy, Péter; Szolgay, Péter
Date: 1995.
Published by: A CNN platform to a discrete-time cellular neural network universal machine chip. (Research report of the Analogical and Neural Computing Laboratory DNS-12-1995.)

Real-life application case studies using CMOS 0.8 mm CNN universal chip: analogic algorithm for motion detection and texture segmentation

Authors: Földesy, Péter; Zarándy, Ákos; Szolgay, Péter; Szirányi, Tamás
Date: 1996.
Published by: 1996 fourth IEEE international workshop on Cellular Neural Networks and their applications proceedings. CNNA-96. Seville, 1996. (Page: 3)

The computational infrastructure of analogic CNN computing - Part I: The CNN-UM chip prototyping system

Authors: Roska, Tamás; Zarándy, Ákos; Zöld, S.; Földesy, Péter; Szolgay, Péter
Date: 1999.
Published by: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS (Page: 2)

Fault-tolerant design of analogic CNN templates and algorithms - Part I: The binary output case

Authors: Földesy, Péter; Kék, László; Zarándy, Ákos; Roska, Tamás; Bártfai, Gusztáv
Date: 1999.
Published by: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS (Page: 3)

CNN chip prototyping and development systems

Authors: Zarándy, Ákos; Roska, Tamás; Szolgay, Péter; Zöld, S.; Földesy, Péter; Petrás, István
Editor: Roska, T
Date: 1999.
Published by: Design automation day on cellular visual microprocessor. Stresa, 1999. (Page: 6)

The computational infrastructure for cellular visual microprocessors

Authors: Szolgay, Péter; Zarándy, Ákos; Zöld, S.; Roska, Tamás; Földesy, Péter; Kék, László; Kozek, T.; László, K.; Petrás, István; Rekeczky, Csaba; Szatmári, István; Bálya, Dávid
Date: 1999.
Published by: MicroNeuro '99. Proceedings of the seventh international conference on microelectronics for neural, fuzzy, and bio-inspired systems. Granada, 1999. (Page: 5)

Fault tolerant CNN template design and optimatization based on chip measurements

Authors: Földesy, Péter; Kék, László; Roska, Tamás; Zarándy, Ákos; Bártfai, Gusztáv
Editor: Tavsanoglu, V
Date: 1998.
Published by: 1998 fifth IEEE international workshop on cellular neural networks and their applications. CNNA 98. Proceedings. London, 1998 (Page: 4)

On the chip implementation of analogic algorithms for optical detection of some layout errors of printed circuit boards

Authors: Tömördi, K.; Földesy, Péter; Szolgay, Péter
Editor: Tavsanoglu, V
Date: 1998.
Published by: 1998 fifth IEEE international workshop on cellular neural networks and their applications. CNNA 98. Proceedings. London, 1998. (Page: 1)

Fault tolerant design of analogic CNN templates and algorithms. Part I: The binary output case.(Research report of the Analogical and Neural Computing Laboratory, DNS-3-1998.)

Authors: Földesy, Péter; Kék, László; Zarándy, Ákos; Roska, Tamás; Bártfai, Gusztáv
Date: 1998.
Published by: Fault tolerant design of analogic CNN templates and algorithms. Part I: The binary output case.(Research report of the Analogical and Neural Computing Laboratory, DNS-3-1998.)

0.8-?m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage

Authors: Domínguez-Castro, R.; Espejo, S.; Rodríguez-Vázquez, A.; Carmona, RA; Földesy, Péter; Zarándy, Ákos; Szolgay, Péter; Szirányi, Tamás; Roska, Tamás
Date: 1997.
Published by: IEEE JOURNAL OF SOLID-STATE CIRCUITS (Page: 1)